/**
 * Wire Data type
 * 线数据类型
 *
 * In Verilog 1995, default data type is net and its width is always 1 bit. In Verilog 2001 the width is adjusted automatically.
 * 在Verilog 1995中，默认的数据类型是net，其宽度总是1位。在Verilog 2001中，宽度是自动调整的。
 * 
 * In Verilog 2001, we can disable default data type by `default net_type none, This basically helps in catching the undeclared wires.
 * 在Verilog 2001中，我们可以禁用默认数据类型`default net_type none，这基本上有助于捕获未声明的连接。
 *
 * Register Data type
 * 寄存器数据类型
 *
 * Register data type is called variable, as it created a lot of confusion for beginners. Also it is possible to specify an initial value for the register/variable data type. Reg data type can also be declared as signed.
 * 注册数据类型称为变量，因为它给初学者造成了很多混淆。也可以为寄存器/变量数据类型指定一个初始值。Reg数据类型也可以声明为签名。
 */

module v2k_reg();

// v2k allows to init variables
// v2k允许初始化变量
reg a = 0;
// Here only last variable is set to 0, i.e d = 0
// 这里只有最后一个变量被设置为0，即d = 0
// Rest b, c are set to x
// b, c被设为x
reg b, c, d = 0;
// reg data type can be signed in v2k
// reg数据类型可以在v2k中定义为有符号
// We can assign with signed constants
// 我们可以用有符号的常量赋值
reg signed [7:0] data = 8'shF0;

// Function can return signed values
// 函数可以返回有符号的值
// Its ports can contain signed ports
// 它的端口可以包含有符号的端口
function signed [7:0] adder;
  input a_in;
  input b_in;
  input c_in;
  input signed [7:0] data_in;
  begin
    adder = a_in + b_in + c_in + data_in;
  end
endfunction

endmodule
